psajna/Gigatron_MiSTer
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Gigatron TTL Computer for MiSTer FPGA
35 commits 1 branch 0 tags 8.8 MiB
  • C++ 65.2%
  • C 20.2%
  • SystemVerilog 6.7%
  • Verilog 5.5%
  • VHDL 1.8%
  • Other 0.6%
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Paul Sajna 1686295d19 delete old sim junk
2022-04-20 12:30:28 -07:00
releases beta release 2021-05-24 13:21:56 -07:00
rtl Verilator work 2022-04-20 18:22:39 +02:00
sys update sys 2021-03-05 19:26:17 -08:00
verilator remove erroneous submodule 2022-04-20 12:23:38 -07:00
.gitignore verilator update 2022-04-20 12:18:18 -07:00
clean.bat WIP porting 2020-12-22 11:09:26 -08:00
files.qip partially working keyboard, no extended keycodes or ctrl/alt/shift/etc. 2021-05-23 18:35:57 -07:00
Gigatron.qpf WIP porting 2020-12-22 11:09:26 -08:00
Gigatron.qsf Verilator work 2022-04-20 18:22:39 +02:00
Gigatron.sdc WIP porting 2020-12-22 11:09:26 -08:00
Gigatron.srf WIP porting 2020-12-22 11:09:26 -08:00
Gigatron.sv Verilator work 2022-04-20 18:22:39 +02:00
Gigatron_Q13.qpf WIP porting 2020-12-22 11:09:26 -08:00
Gigatron_Q13.qsf WIP porting 2020-12-22 11:09:26 -08:00
Gigatron_Q13.srf WIP porting 2020-12-22 11:09:26 -08:00
LICENSE WIP porting 2020-12-22 11:09:26 -08:00
MENLO_COPYRIGHT.TXT more WIP 2021-01-17 15:01:20 -08:00
Readme.md more WIP 2021-01-17 15:01:20 -08:00

Readme.md

Gigatron_MiSTer

WIP. Port of https://github.com/menloparkinnovation/menlo_gigatron by menloparkinnovation. Used under MIT License. Ported by sajattack.